1. Technical Field
The present invention relates to a semiconductor memory apparatus, and more particularly, to a semiconductor memory apparatus including a data transmission device.
2. Related Art
Data input operations in a synchronous semiconductor memory apparatus are typically performed in synchronization with an internal clock signal which is generated based on an external clock signal. The synchronous semiconductor memory apparatus uses a pre-fetch scheme and may input multi-bit data in response to one-time input command. The pre-fetch scheme is a data input method by which serial multi-bit data sequentially inputted to each data pad in response to one-time input command is temporarily stored in a data transmission device, and then is applied to a plurality of input/output lines at once. A 2-bit pre-fetch scheme, a 4-bit pre-fetch scheme and an 8-bit pre-fetch scheme are used depending on the type of the synchronous semiconductor memory apparatus. For example, in the case of using the 8-bit pre-fetch scheme, 8-bit data is serially inputted through data pads in response to a one-time input command. Such 8-bit serial data is stored in the data transmission device until the least significant bit (LSB) of the 8-bit serial data is inputted, and then is simultaneously applied to 8 parallel input/output lines in response to an activation of an enable signal. The enable signal is activated once in response to the one-time input command. As described above, the multi-bit pre-fetch type semiconductor memory apparatus includes a data transmission device that latches serially inputted data to be applied to the parallel input/output lines, and simultaneously applies the data to the input/output lines in response to the enable signal GIO_en (see FIG. 1).
FIG. 1 is a block diagram of a conventional data transmission device in a semiconductor memory apparatus. The conventional data transmission device receives input data Din from a single local data input/output line, and transmits the input data to a plurality of global output data lines GIO1, GIO2. The conventional data transmission device includes a plurality of write data generation blocks, which generate write data from input data Din and latch the write data, and a plurality of loading blocks which apply the write data to respective input/output lines. FIG. 1 illustrates the 2 bit pre-fetch scheme which includes two write data generation blocks 11 and 12 and two loading blocks 21 and 22.
The data transmission device shown in FIG. 1 includes the first and second write data generation blocks 11 and 12 that perform serial input/output operations, and the first and second loading blocks 21 and 22. The first loading block 21 is connected between the first write data generation block 11 and a first input/output line GIO1, and the second loading block 22 is connected between the second write data generation block 12 and a second input/output line GIO2. The first write data generation block 11 latches the input data Din in response to a data strobe signal DQS inputted from outside, and outputs first write data Wdata1. Since the serial input/output operation is performed between the first write data generation block 11 and the second write data generation block 12, the first write data Wdata1 serves as an input of the second write data generation block 12. In FIG. 1 which illustrates the 2-bit pre-fetch scheme, the input data Din is a signal containing the sequentially inputted two bits in total. When the data strobe signal DQS is initially activated, the first bit of the input data Din is latched by the first write data generation block 11 and the first write data Wdata1 is generated from the first bit. When the data strobe signal DQS is subsequently activated, the first write data Wdata1 is latched by the second write data generation block 12 and the second write data Wdata1 is generated from the first write data Wdata1. At this time, the second bit of the input data Din is latched by the first write data generation block 11 and the first write data Wdata1 is generated from the second bit. As the data strobe signal DQS is activated twice, the 2-bit input data Din is latched to be the first write data Wdata1 and the second write data Wdata2. The input data Din serially inputted based on the activation of the data strobe signal DQS is latched to be the first write data Wdata1 and the second write data Wdata2 (that is, parallel data) by the first write data generation block 11 and the second write data generation block 12. When the enable signal GIO_en is activated, the first write data Wdata1 and the second write data Wdata2 latched by the first write data generation block 11 and the second write data generation block 12 are applied to the first input/output line GIO1 and the second input/output line GIO2 by the first loading block 21 and the second loading block 22, respectively. Based on the operational principle described above, the data transmission device having the 2-bit pre-fetch scheme requires two periods of the data strobe signal DQS in order to apply the sequentially inputted 2-bit input data Din to the first input/output line GIO1 and the second input/output line GIO2. Since the data strobe signal DQS typically has a period equal to that of an external clock, the data transmission device having the 2-bit pre-fetch scheme requires time corresponding to two periods based on the external clock in order to apply the sequentially inputted 2-bit input data Din to the first input/output line GIO1 and the second input/output line GIO2. Thus, a semiconductor memory apparatus including the data transmission device shown in FIG. 1 needs to have the operation time longer than two periods of the external clock from an input command to the next input command. The time from the input command to the next input command varies depending on the pre-fetch scheme. For example, a data transmission device having the 8-bit pre-fetch scheme needs to have the operation time longer than eight periods of the external clock from the input command to the next input command. If a double data rate (DDR) scheme is used in the semiconductor memory apparatus as well as a pre-fetch scheme, the required time from one input command to the next input command may be reduced to ½. For example, a semiconductor memory apparatus using the 8-bit pre-fetch scheme and the DDR scheme needs to have the operation time longer than four periods of the external clock from one input command to the next input command.
FIG. 2 is a circuit diagram of the first write data generation block and the first loading block shown in FIG. 1. Since the second write data generation block 12 and the second loading block 22 may have the same configurations as those of the first write data generation block 11 and the first loading block 21, a detailed description thereof will be omitted. The first write data generation block 11 latches the input data Din in response to the data strobe signal DQS inputted from outside, and outputs the first write data Wdata1. The first loading block 21 applies the first write data Wdata1 to the first input/output line GIO1 in response to the enable signal GIO_en. The write data generation block is coupled in series to the loading block and may be used for the multi-bit pre-fetch scheme as in the example of FIG. 1. For example, the 8-bit pre-fetch scheme needs 8 pairs of the write data generation block and the loading block. The first write data generation block 11 of FIG. 2 applies the input data Din to a first latch L1 at a falling edge of the data strobe signal DQS, and applies data in the first latch L1 to a second latch L2 at a rising edge of the data strobe signal DQS. That is, the data in the two latches L1 and L2 are shifted every one period of the data strobe signal DQS which swings between a high level and a low level. The data, which is applied to the second latch L2 and stored therein, that is, the first write data Wdata1 serves as input data Wdata1 of the second write data generation block 12 (see FIG. 1) of the next stage, which is connected in series to the first write data generation block 11. When the enable signal GIO_en is activated, the first loading block 21 applies the first write data Wdata1 latched by the second latch L2 to the first input/output line GIO1. In the case of the 8-bit pre-fetch scheme, in order for the respective write data generation blocks to latch all 8-bit data of the data strobe signal DQS, the data strobe signal DQS needs to be swung between a high level and a low level eight times. Furthermore, since the data strobe signal DQS is synchronized with an external clock signal, a semiconductor memory apparatus using the 8-bit pre-fetch scheme has to follow the operational rule that each input command may not be inputted in eight clocks (four clocks in the case of using the DDR scheme with the 8-bit pre-fetch scheme). FIG. 3 is a signal waveform diagram explaining the operational rule.
FIG. 3 shows waveforms in which data D0 to D7 are serially inputted to a plurality of data pads DQ<0> to DQ<3> in response to input commands WT0 and WT1 inputted every four period of a clock signal CLOCK in a semiconductor memory apparatus using both the 8-bit pre-fetch scheme and the DDR scheme. Furthermore, FIG. 3 shows a waveform ‘a’ in which the 8-bit data is simultaneously applied to an input/output line in a parallel manner in response to the enable signal GIO_en (see FIG. 1) after all the 8-bit data is serially applied.
The semiconductor memory apparatus is executed through data input/output operations from and to memory cells. In order to verify normal functioning of a cell during manufacturing of a semiconductor memory apparatus, it is determined whether the cell is capable of performing normal operations by applying a stress to the cell, or performing the data input/output operation with respect to the cell without applying a stress. Such a test is called a programmable stress test. The programmable stress test is performed by loading the semiconductor memory apparatus onto test equipment, and performing the data input/output operation with respect to the cell. As the semiconductor memory apparatus is highly integrated and operates at a high speed, the test time of the programmable stress test increases more and more. The programmable stress test is used to determine whether the semiconductor memory apparatus is capable of performing normal operations by conducting the data input/output operation with respect to the cell. As the semiconductor memory apparatus is highly integrated, the large number of cells are included in the semiconductor memory apparatus. Therefore, the programmable stress test time also increases. Furthermore, as the semiconductor memory apparatus operates at a high speed, the semiconductor memory apparatus may have to operate in response to a faster clock signal. However, a clock signal inputted from a programmable stress test equipment is slower than a high speed clock signal operable in the semiconductor memory apparatus. The programmable stress test equipment inputs the clock signal, which may be slower than the high speed clock signal operable in the semiconductor memory apparatus, to the semiconductor memory apparatus by the following two reasons. First, when a fail in the cell has occurred during the data input/output operation, it is necessary to avoid a situation in which it may not be possible to determine whether the reason for the fail is caused by the lack of a margin for a high speed operation or the abnormal operation of the cell, that is, it is necessary to ensure the reliability of the programmable stress test. Second, since the semiconductor memory apparatus operating at a higher speed is tested using a traditional programmable stress test equipment, the high speed clock signal operable in the semiconductor memory apparatus may be faster than a clock signal inputted from the programmable stress test equipment.
At the present time, the period of a clock signal operable in a DDR3 semiconductor memory apparatus is approximately 1 ns to approximately 2 ns. However, the period of a clock signal inputted from the programmable stress test equipment to the semiconductor memory apparatus is approximately 16 ns. Since the period of the clock signal used for the programmable stress test may be longer than that of the high speed clock signal operable in the semiconductor memory apparatus, and an input command may not be inputted in four periods of a clock according to the 8-bit pre-fetch scheme and the DDR scheme as described above, the programmable stress test time is inefficiently increased. Such a problem becomes severer as the semiconductor memory apparatus is highly integrated and operates at a high speed. Since the increase in the test time may cause an increase in the production time of the semiconductor memory apparatus, the semiconductor memory apparatus has disadvantages in terms of the production cost and manufacturing efficiency.